In an active matrix display device, many display pixels are arranged in a matrix, and an image is displayed by the light intensity being controlled for every pixel in accordance with a picture signal. In recent years, demands for a liquid crystal display device that is an active matrix display device using a liquid crystal element are increasing due to advantages such as light weight, thinness, and low power consumption. In order to achieve light weight, thinness, low power consumption, and the like further, an active matrix display device using an organic electro-luminescence element (hereinafter, abbreviated as “organic EL element”) in which a backlight required in a liquid crystal display device is unnecessary has been developed (for example, see Patent Document 1).
FIG. 33 is a circuit diagram showing the configuration of a pixel circuit of a conventional active matrix display device. As shown in FIG. 33, the conventional active matrix display device includes a plurality of pixel circuits 112a and 112b, a plurality of gate signal wires 116a and 116b, and a plurality of source signal wires 118. The gate signal wires 116a and 116b are driven by a gate driver (omitted in the drawing), and the source signal wires 118 are driven by a source driver (omitted in the drawing).
The pixel circuit 112a includes a drive transistor 111a, an organic EL element 114a, a switch 117a, and a storage capacitance 119a to form a display pixel. The pixel circuit 112b is configured in a similar manner and behaves in a similar manner to the pixel circuit 112a. Other pixel circuits (omitted in the drawing) are similar.
Writing of a picture signal in each pixel is performed by switches 117a and 117b. That is, the switches 117a and 117b are caused to be in a conducted state in order, and a voltage corresponding to the picture signal applied to the source signal wire 118 is stored in storage capacitances 119a and 119b. Even if the switches 117a and 117b come to a non-conducted state, drive transistors 111a and 111b supply current in accordance with the voltage stored in the storage capacitances 119a and 119b to organic EL elements 114a and 114b for one frame period, and each pixel emits light with predetermined luminance.
FIG. 34 is a timing diagram showing the voltage waveforms of the gate signal wire and the source signal wire shown in FIG. 33. For example, in the case of capturing a picture signal into the pixel circuit 112a from the source signal wire 118, it is necessary that a voltage SV of the source signal wire 118 be a predetermined voltage when a voltage GV of the gate signal wire 116a changes and the switch 117a is in a conducted state, as shown in FIG. 34.
At time t1 in an example shown in FIG. 34, the voltage SV of the source signal wire 118 has dropped from a predetermined first voltage Vdw to a predetermined second voltage Vdk, the predetermined second voltage Vdk is written in the pixel circuit 112a, and the pixel emits light with a predetermined luminance. Thus, change in the voltage SV of the source signal wire 118 has to be completed by time t2 that is one horizontal scanning period minus a falling period of the voltage GV of the gate signal wire 116a. 
However, when the load capacitance of the source signal wire 118 is large, the rate of change in the voltage SV of the source signal wire 118 is slow, and there are cases where the voltage SV of the source signal wire 118 does not become the predetermined second voltage Vdk even at the time t2. In this case, the voltage of the source signal wire 118 at the time t2 is written in the pixel circuit 112a, the pixel emits light with a luminance different from the predetermined luminance, and a favorable image cannot be displayed.
The rate of change in the voltage of the source signal wire 118 is determined by the load on the source signal wire 118, and changes in accordance with the time constant determined by the resistance value of the source signal wire 118 multiplied by the capacitance value of the source signal wire 118.
As shown with a broken line in FIG. 33, the source signal wire 118 is formed, as parasitic capacitance, with a wiring capacitance 115 generated between wiring of the source signal wire 118 and another layer and channel capacitances 113a and 113h generated between the gate and drain or between the gate and source of the switches 117a and 117b for capturing a picture signal into the pixel circuits 112 and 112b from the source signal wire 118. The wiring capacitance 115 is determined by the wiring length and the wiring width of the source signal wire 118, and the channel capacitances 113a and 113b are determined by the number of the switches 117a and 117b connected to the same source signal wire 118 and the shape of a transistor forming the switches 117a and 117b. With these capacitances, the capacitance of the source signal wire 118 increases, and the rate of change in the voltage of the source signal wire 118 decreases.
In an active matrix display device using a liquid crystal element, an organic EL element, or the like, there is an increase in the load capacitance of the source signal wire 118 due to an increase in screen size or an increase in the number of vertical lines, and it is becoming increasingly difficult to write the voltage of a desired picture signal in a pixel circuit in a predetermined period (one horizontal scanning period).
In the case where the number of pixel rows has increased due to the increase in resolution of a display screen, the rate of change in the voltage of the source signal wire decreases, and it becomes further difficult to write a picture signal accurately. In the case where the number of pixel columns has increased due to an increase in resolution of the display screen, the arrangement pitch of the source signal wire and the pixel circuit narrows, and therefore a leak current occurs. As a result, a vertical crosstalk occurs, an unnecessary image similar to a strip being drawn in the vertical direction is displayed, and the display quality decreases.
Patent Document 1: Japanese Patent Application Laid-open No. H8-241048